This application relies for priority upon Korean Patent Application No. 2001-13620, filed on Mar. 16, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to the field of a direct memory access (DMA) transfer system, and more particularly to a device for high-speed data transfer in a DMA controller.
A direct memory access (to be referred to as DMA hereinafter) transfer system is one of the data transfer methods carried out directly between a main memory and an input/output device without the need for control operation by a central processing unit (CPU). In the DMA transfer system, during process of input/output command signals by the CPU, the data is directly transmitted to an associated device through the input/output device.
It is necessary to add a system bus to a DMA module such as DMA controller to accommodate the DMA transfer system. The DMA controller processes some of the functions related to system control operation, rather than the CPU. In order perform this operation, when a data block is in need of being written therein or being read therefrom, the CPU supplies command signals to the DMA controller, where the command signals include information for a designation of write-in/read-out operation, an address of the input/output device, an initial address for writing/reading data from memory cells in a memory device, and the number of words to be written in or read out. After providing command signals, the CPU continues to process other, unrelated, operations, such that the DMA controller, and not the CPU, carries out the input/output operations. The DMA controller directly transmits entire data blocks word by word, without the need for control operation by the CPU. When data transfer operation is completed, the DMA module provides an interrupt signal to the CPU, to inform the CPU of the completion of data transfer. IN this manner, the CPU is needed only at the beginning and end of data transfer. The DMA transfer method is disclosed in U.S. Pat. Nos. 5,669,014; 5,613,162; 5,590,286; 5,513,374.
As well known to this art, DMA transfer generally includes two modes of DMA transfer, single mode and burst mode. If a precedence interrupt is generated, the single mode first performs the interrupt operation, and then transmits data. In contrast, the burst mode transmits data completely without being interrupted during the transfer operation of an entire data block. Transfer capacity of the system bus of the DMA controller thus depends on the application of the burst mode. Contemporary DMA controllers generally apply the burst mode, and are operable with various sizes of transmitted data (e.g. byte, half-word, and a word) and various burst lengths (e.g. 4, 8, and 16 length).
However, the burst mode is operable only in a case where the data transfer counter value can be evenly divided by the burst length, that is, without a remainder. As a result, in the case that the data transfer counter value cannot be completely divided by the burst length, there is a problem of functional limit that the DMA controller cannot be operable with the burst mode. To solve this problem, the burst mode is applied by programming data transfer counter value previously calculated. However, it is troublesome that programmers have to calculate the data transfer counter value in advance, and to program by each data length.
The object of the present invention is to provide a device capable of improving data transfer speed by converting a DMA transfer operation mode to a burst mode and/or a single mode automatically regardless of the data transfer counter value.
According to the present invention, a direct memory access controller (DMA) includes a system bus interface, first to fourth registers, a register control circuit, and a burst/single mode control circuit. The system bus interface carries out interfacing with an address of an input/output device, an address for writing/reading data from memory cells in a memory device, the data transfer counter value to be written in/read out therefrom, and control signal for a DMA transfer operation. The first register stores the address of the input/output device, the second register stores the initial address of the data to be written in/read out from the memory cell, the third register stores the data transfer counter value, and the fourth register stores the control signal. The register control circuit loads the addresses, the data transfer counter value, and the control signal from the system bus interface on the first to fourth registers. Further, the burst/single mode control circuit receives the data transfer counter value and the control signal from the third and fourth registers, and automatically converts a DMA transfer operation mode to a burst mode or a single mode, and then performs the DMA transfer operation in accordance with the converted DMA transfer operation mode.
In a preferred embodiment, the burst/single mode control circuit carries out the burst mode DMA transfer operation a number of times corresponding to a quotient which is the result that the data transfer counter value divided by the burst length, and also carries out the single mode DMA transfer operation a number of times corresponding to the remainder of the division.
The burst mode and single mode DMA transfer operations are successively carried out by the burst/single mode control circuit without the need for intervening control operations by the CPU.